Intel 8080: Разлика между версии
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The '''Intel 8080''' was an early [[microprocessor]] designed and manufactured by [[Intel]]. The [[8-bit]] [[central processing unit|CPU]] was released in April 1974 running at 2 [[megahertz|MHz]] (at up to 500,000 [[instructions per second]]), and is generally considered to be the first truly usable microprocessor CPU design. It was implemented in [[NMOS logic|NMOS]]. |
The '''Intel 8080''' was an early [[microprocessor]] designed and manufactured by [[Intel]]. The [[8-bit]] [[central processing unit|CPU]] was released in April 1974 running at 2 [[megahertz|MHz]] (at up to 500,000 [[instructions per second]]), and is generally considered to be the first truly usable microprocessor CPU design. It was implemented in [[NMOS logic|NMOS]]. |
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==Description== |
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===Programming model=== |
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The Intel 8080 was the successor to the [[Intel 8008]]; this was due to its being [[assembly language]] [[source-compatibility|source-compatible]], since it used the same [[instruction set]] developed by [[Computer Terminal Corporation]]. The 8080's large 40 pin [[dual in-line package|DIP]] packaging permitted it to provide a 16-bit [[address bus]] and an 8-bit [[data bus]], allowing easy access to 64 [[kilobyte]]s of memory. (Every instruction of the 8080's instruction set has a direct equivalent in the current [[Intel Core 2]]'s larger instruction set, although the opcode values are different.) |
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====Registers==== |
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The processor had seven 8-bit [[processor register|registers]], six of which could be combined into three 16-bit register pairs (BC, DE and HL). It also had an 8-bit accumulator, a 16-bit [[Stack-based memory allocation|stack pointer]] to memory (replacing the 8008's internal [[stack (data structure)|stack]]), and a 16-bit [[program counter]]. |
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====Commands==== |
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Most of the 8-bit operations were possible between the [[Accumulator (computing)|accumulator]] and either one of the registers or the memory cell, indexed by the 16-bit value of the register pair HL. Moving operations were supported between any two registers, or between any register and the HL-indexed memory cell. Due to the highly regular machine code format for MOV commands, the opcodes included those for moving a byte from a given register into the same register (MOV A,A , for instance). These commands were seldom used, however, unless programmed delays were needed. What would have been instruction to move from the HL-indexed memory cell into the same memory cell (i.e., MOV M,M) instead was [[HLT]] (for halt). [[HLT]] halted the processor until external reset or interrupt signals were received. |
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All processor commands were coded by one byte, but some of them were followed by one or two bytes of data, a memory address, or a port number. The register-to-register data-move commands were all coded by one byte, making up about a quarter of the commands in the processor-command system. The processor had eight one-byte commands to call the subroutines located at the fixed addresses 0000h, 0008h, 0010h, ... 0038h (RST). These commands were frequently used in the interrupt-handling or system-library calls. |
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The most sophisticated command (and the longest to execute) was XTHL, which was used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer. |
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====16-bit operations==== |
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Despite the fact that the 8080 was generally an 8-bit processor, it was also able to load immediate any register pair (LXI), increment or decrement any register pair (INX, DCX), add any register pair to the value in HL (DAD), switch HL with DE (XCHG) and perform a 16-bit arithmetical left shift of HL (DAD H) with one command. Hence some 16-bit operations were already possible. The only 16 bit instructions to affect the flags are the DADs, which set the CY (carry) flag. |
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===Input/output scheme=== |
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====Input output port space==== |
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The 8080 supported up to 256 [[input/output]] (I/O) ports, accessed from programs via dedicated I/O instructions—each instruction taking an I/O port address as its operand. This scheme—using a separate I/O address space—is now less commonly used than [[memory map]]ping of I/O ports/devices. At the time of the 8080's launch, this I/O mapping scheme was seen as an advantage, as it freed up the processor's limited number of address pins for the memory address space. In most other CPU architectures, however, the mapping of I/O ports in a common address space both for memory and I/O, gave a simpler instruction set; no need for separate I/O instructions. The 8080-style I/O port scheme continued into the [[Intel 8085]] and [[x86]] families of microprocessors, as well as the Zilog Z80 series. |
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====Stack space==== |
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One of the bits in the processor state word (see below) was indicating that the processor is accessing data from the stack. Using this signal, it was possible to implement a separate stack memory space. However this feature was seldom used. |
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====Shared memory implementations==== |
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The 8080 has shared control signals for reading and writing both memory and I/O ports. In basic computers, the 8080 was frequently connected using a shared memory map, accessing ports as memory cells. In such machines, the specialised I/O commands were either not used or, in applications with little memory, were used knowing that the processor would clone the 8-bit port address to both the lower and the higher address byte (IN 05h would put the address 0505h on the 16-bit address bus). |
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===The internal state word=== |
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For more advanced systems, during one phase of its working loop the processor set its "internal state byte" on the data bus. This byte contains flags which indicate whether the memory or I/O port is accessed and whether it was necessary to handle an interrupt. |
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The interrupt system state (enabled or disabled) was also output on a separate pin. For simple systems, where the interrupts were not used, it is possible to find cases where this pin is used as an additional single-bit output port (the popular [[Radio86RK]] computer made in USSR, for instance). |
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===Pin usage=== |
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The address bus had its own 16 pins, and the data bus had 8 pins that were possible to use without any multiplexing. Using the two additional pins (read and write signals), it was possible to assemble simple microprocessor devices very easily. Only the separate IO space, interrupts and DMA required additional chips to decode the processor pin signals. However the processor load capacity was limited, and even simple computers frequently contained bus amplifiers. |
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The processor required three power sources (-5, +5 and +12 Volt(V)) and two non-interlacing high-amplitude synchronization signals. However at least the late Soviet version КР580ВМ80А was able to work with a single +5 V power source, the +12 V pin being connected to +5 V and the -5 V pin to ground. The processor consumed about 1.3 watts (W) of power. |
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The pinout table, from the chip's accompanying documentation, described the pins as follows: |
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<table border="1" > |
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<tr> |
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<th>Pin number</th> |
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<th>Signal</th> |
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<th>Type</th> |
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<th>Comment</th> |
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</tr> |
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<tr> <td>1</td><td>A10</td> |
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<td>Output</td><td>Address bus 10</td></tr> |
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<tr> <td>2</td><td>GND</td> |
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<td>-</td><td>Ground</td></tr> |
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<tr> <td>3</td><td>D4</td> |
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<td rowspan="8">Bidirectional</td> |
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<td rowspan="8">Bidirectional data bus. The processor also transiently sets here the "processor state", providing information that the processor is currently doing: |
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*D0 reading interrupt command. In response to the interrupt signal, the processor was reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provided the subroutine call command (CALL or RST), transferring control to the interrupt handling code. |
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*D1 reading (low level means writing) |
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*D2 accessing stack (probably a separate stack memory space was initially planned) |
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*D3 doing nothing, has been halted by the [[HLT]] command |
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*D4 writing data to an output port |
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*D5 reading the first byte of an executable command |
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*D6 reading data from an input port |
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*D7 reading data from memory |
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</td> |
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</tr><tr> |
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<td>4</td><td>D5</td></tr> |
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<tr> <td>5</td><td>D6</td></tr> |
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<tr> <td>6</td><td>D7</td></tr> |
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<tr> <td>7</td><td>D3</td></tr> |
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<tr> <td>8</td><td>D2</td></tr> |
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<tr> <td>9</td><td>D1</td></tr> |
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<tr> <td>10</td><td>D0</td></tr> |
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<tr> <td>11</td><td>-5 V</td> |
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<td>-</td><td>The -5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged.</td></tr> |
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<tr> <td>12</td><td>R</td> |
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<td>Input</td><td>Reset. The signal forces execution of commands, located at address 0000. The content of other processor registers is not modified. This is an inverting input (the active level being logical 0)</td></tr> |
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<tr> <td>13</td><td>DMA</td> |
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<td>Input</td><td>Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state.</td></tr> |
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<tr> <td>14</td><td>INT</td> |
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<td>Input</td><td>Interrupt request</td></tr> |
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<tr> <td>15</td><td>CLC2 |
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<td>Input</td><td>The second phase of the clock generator signal</td></tr> |
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<tr> <td>16</td><td>ACK INT</td> |
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<td>Output</td><td>The processor had two commands for setting 0 or 1 level on this pin. The pin normally was supposed to be used for interrupt control. However in simple computers it was sometimes used as a single bit output port for various purposes.</td></tr> |
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<tr> <td>17</td><td>RD</td> |
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<td>Output</td><td>Read (the processor reads from memory or input port)</td></tr> |
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<tr> <td>18</td><td>WR</td> |
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<td>Output</td><td>Write (the processor writes to memory or output port). This is an inverted output, the active level being logical zero.</td></tr> |
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<tr> <td>19</td><td>S</td> |
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<td>Output</td><td>Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide additional information for supporting the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register.</td></tr> |
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<tr> <td>20</td><td>5 V</td><td>-</td><td>The + 5 V power supply</td></tr> |
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<tr><td colspan="4"><hr></td></tr> |
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<tr> <td>21</td><td>ACK DMA</td> |
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<td>Output</td><td>Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus</td></tr> |
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<tr> <td>22</td><td>CLC1</td> |
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<td>Input</td><td>The first phase of the clock generator signal</td></tr> |
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<tr> <td>23</td><td>RDY</td> |
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<td>Input</td><td>Wait. With this signal it was possible to suspend the processor's work. It was also used to support the hardware-based step-by step debugging mode.</td></tr> |
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<tr> <td>24</td><td>WAIT</td> |
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<td>Output</td><td>Wait (indicates that the processor is in the waiting state)</td></tr> |
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<tr> <td>25</td><td>A0</td> |
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<td rowspan="3">Output</td> |
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<td rowspan="3">Address bus</td></tr> |
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<tr> <td>26</td><td>A1</td></tr> |
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<tr> <td>27</td><td>A2</td></tr> |
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<tr> <td>28</td><td>12 V</td> |
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<td>-</td><td>The +12 V power supply. This must be the ''last'' connected and first disconnected power source.</td></tr> |
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<tr> <td>29</td><td>A3</td> |
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<td rowspan="12">Output</td> |
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<td rowspan="12">The address bus, can switch into high impedance state on demand</td></tr> |
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<tr> <td>30</td><td>A4</td></tr> |
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<tr> <td>31</td><td>A5</td></tr> |
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<tr> <td>32</td><td>A6</td></tr> |
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<tr> <td>33</td><td>A7</td></tr> |
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<tr> <td>34</td><td>A8</td></tr> |
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<tr> <td>35</td><td>A9</td></tr> |
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<tr> <td>36</td><td>A15</td></tr> |
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<tr> <td>37</td><td>A12</td></tr> |
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<tr> <td>38</td><td>A13</td></tr> |
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<tr> <td>39</td><td>A14</td></tr> |
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<tr> <td>40</td><td>A11</td></tr> |
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</table> |
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Literature, used for this table: |
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* http://tehno-doc.nm.ru/mikroshem_rus/kr580/kr580vm80a.html |
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* http://www.radiomaster.ru/stati/radio/k580/14_k580.php |
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==Physical implementation== |
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The 8080 [[integrated circuit]] used enhancement load [[nMOS logic|nMOS]] gates and was manufactured in a process using a minimum feature size of 6 µm. A single layer of metal was used to [[Electrical connection|interconnect]] the approximately 6000 transistors in the design (the higher [[Electrical resistance|resistance]] [[Polycrystalline silicon|polysilicon]] layer required to implement transistor gates was also used for some interconnects). The [[Die preparation|die]] size was approximately 20 mm². |
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==The industrial impact== |
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===Applications and successors=== |
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The 8080 was used in many early microcomputers, such as the [[Altair 8800|MITS Altair 8800]] Computer, [[Processor Technology]] [[SOL-20]] Terminal Computer and [[IMSAI 8080]] Microcomputer, forming the basis for machines running the [[CP/M]] operating system (the later, fully compatible and more capable, [[Zilog Z80]] processor would capitalize on this, with Z80 & CP/M becoming the dominant CPU & OS combination of the period much like [[x86]] & [[MS-DOS]] for the PC a decade later). The first [[single-board computer|single-board microcomputer]] (see the May 1976 issue of Radio-Electronics) called the "dyna-micro" was based on the Intel C8080A, and also used Intel's first EPROM, the C1702A. The dyna-micro was re-branded by E&L Instruments of Derby, CT in 1976 as the "MMD-1" (Mini-Micro Designer 1) and was made famous as the example microcomputer in the very popular 8080 "BugBook" series of the time. One of the early uses of the 8080 was made in the late 1970s by Cubic-Western Data of San Diego, CA in it's Automated Fare Collection Systems custom designed for mass transit systems such as BART and others around the world. An early industrial use of the 8080 was as the "brain" of the DatagraphiX Auto-COM (Computer Output Microfiche) line of products which took large amounts of user data from reel-to-reel tape and imaged it onto microfiche. The Auto-COM instruments also included an entire automated film cutting, processing, washing, and drying sub-system - quite a feat, both then and in the 21st century, to all be accomplished successfully with only an 8-bit microprocessor running at a clock speed of less than 1MHz with a 64K byte memory limit. In addition, several early [[Arcade game|arcade]] [[video game]]s were built around the 8080 microprocessor. ''[[Space Invaders]]'' was perhaps the most popular such title. |
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Shortly after the launch of the 8080, the [[Motorola 6800]] competing design was introduced, and after that, the [[MOS Technology 6502]] variation of the 6800. [[Zilog]] introduced the [[Zilog Z80|Z80]], which had a compatible machine-language instruction set and initially used the same assembly language as the 8080, but for legal reasons, Zilog developed a syntactically-different alternative assembly language for the Z80. At Intel, the 8080 was followed by the compatible and electrically more elegant [[Intel 8085|8085]], and later by the assembly language compatible 16-bit [[Intel 8086|8086]] and then the 8/16-bit [[Intel 8088|8088]], which was selected by [[IBM]] for its new [[IBM PC|PC]] to be launched in 1981. Later [[NEC]] made a [[NEC V20]] processor (a 8088 clone) which supported 8080 emulation mode. Thus, the 8080, via its [[instruction set architecture|ISA]], made a lasting impact on computer history. |
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The Soviet Union manufactured a complete 8080 analog named KP580ИK80 (later marked as [[KR580VM80A|KP580BM80]]), where even the pins were placed identically. This processor was the base of the Radio86RK ([http://ru.wikipedia.org/wiki/%D0%A0%D0%B0%D0%B4%D0%B8%D0%BE_86%D0%A0%D0%9A Радио 86РК] in Russian), probably the most popular amateur single-board computer in the Soviet Union. Radio86RK's predecessor was the Micro-80 ([http://ru.wikipedia.org/wiki/%D0%9C%D0%B8%D0%BA%D1%80%D0%BE-80 Микро-80] in Russian), and its successor the Orion-128 ([http://ru.wikipedia.org/wiki/%D0%9E%D1%80%D0%B8%D0%BE%D0%BD-128 Орион-128] in Russian) which had a graphical display. Both were built on the KP580 processor. According to some sources, the Soviet analog had two undocumented instructions, specific to itself; however, these were not widely known. |
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Another model compatible with Intel 8080A, named [[MMN8080]], was produced at [[Microelectronica Bucharest]] in [[Romania]]<ref>[http://www.cpu-world.com/info/exUSSR-chips.html CPU-world: Soviet chips and their western analogs<!-- Bot generated title -->]</ref>. |
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===Industry change=== |
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The 8080 also changed how computers were created. When the 8080 was introduced, computer systems were usually created by computer manufacturers such as [[Digital Equipment Corporation]], [[Hewlett Packard]], or [[IBM]]. A manufacturer would produce the entire computer, including processor, terminals, and system software such as compilers and operating system. The 8080 was actually designed for just about any application ''except'' a complete computer system. Hewlett Packard developed the [[HP 2640]] series of smart terminals around the 8080. The [[HP 2647]] was a terminal which ran [[BASIC programming language|BASIC]] on the 8080. |
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[[Microsoft]] would create the first popular programming language for the 8080, and would later acquire [[DOS]] for the [[IBM-PC]]. |
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As the 8080 evolved into the largely compatible x86 family, PCs evolved into workstations and servers of 16, 32 and 64 bits, with advanced memory protection, segmentation, and multiprocessing features, blurring the difference between small and large computers (the [[80286]] and [[80386]]'s [[protected mode]] were important in doing so). The size of chips has grown so that the size and power of large x86 chips is not much different from high end architecture chips, and a common strategy to produce a very large computer is to network many x86 processors. |
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The basic architecture of the 8080 and its successors has replaced many proprietary midrange and mainframe computers, and withstood challenges of technologies such as [[RISC]]. Most computer manufacturers have abandoned producing their own processors below the highest performance points. Though x86 may not be the most elegant, or theoretically most efficient design, the sheer market force of so many dollars going into refining a design has made the x86 family today, and will remain for some time, the dominant processor architecture, even bypassing Intel's attempts to replace it with incompatible architectures such as the [[Intel iAPX 432|iAPX 432]] and [[Itanium]]. |
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==History== |
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[[Federico Faggin]] was the originator of the 8080 architecture in early 1972, proposed it to Intel's management and pushed for its implementation. He finally got the permission to develop it six months later. [[Federico Faggin|Faggin]] hired [[Masatoshi Shima]] from Japan who did the detailed design under his direction. Stan Mazor contributed a couple of instructions to the instruction set. |
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===Patent=== |
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US # 4,010,449. [[March 1]] [[1977]]. [[Federico Faggin]], [[Masatoshi Shima]], Stanley Mazor: "MOS computer employing a plurality of separate chips." |
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==Cultural impact== |
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* [[Asteroid]] (8080) Intel is named as a pun and praise on the name of Intel 8080. [http://cfa-www.harvard.edu/iau/lists/MPNames.html] |
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== See also== |
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* [[CP/M]] |
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== External links == |
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* [http://www.cpu-collection.de/?tn=0&l0=cl&l1=8080 Intel and other manufacturers' 8080 CPU images and descriptions at cpu-collection.de] |
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* [http://www.datasheetarchive.com/search.php?q=8080 Scan of the Intel 8080 data book at datasheetarchive.com] |
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Версия от 15:19, 20 февруари 2008
Шаблон:Infobox Computer Hardware CPU
The Intel 8080 was an early microprocessor designed and manufactured by Intel. The 8-bit CPU was released in April 1974 running at 2 MHz (at up to 500,000 instructions per second), and is generally considered to be the first truly usable microprocessor CPU design. It was implemented in NMOS.